Multilayer ceramic substrates are extensively used for high density packaging of semiconductor integrated circuit chips and other microelectronic elements. As is known to those having skill in the art, the multilayer ceramic substrate includes metallurgy which is buried within the substrate, making possible a very complex and intricate wiring interconnection. A multilayer substrate is described in detail in U.S. Pat. No. 4,245,273 to Feinberg et al. entitled Package for Mounting and Interconnecting a Plurality of Large Scale Integrated Semiconductor Devices.
The multilayer ceramic substrate is fabricated by forming a ceramic slurry, doctor blading the slurry and drying to produce ceramic green sheets. Holes (vias) are punched in the green sheets, and the vias are filled with a conductor. Conductive lines are screened on the green sheets and the green sheets are laminated. The laminated structure is sintered to form a unitary ceramic substrate with a complex internal conductor system including a plurality of conductor filled vias extending to a face thereof.
One face of the multilayer ceramic substrate typically includes an array of capture pads, a respective one of which is electrically connected to a respective one of the conductor filled vias. The capture pads form electrical connections to a multilayer thin film wiring substrate, which is formed on the multilayer ceramic substrate face over the capture pads. Integrated circuit chips are then mounted on the multilayer wiring substrate, opposite the multilayer ceramic substrate. Alternatively, integrated circuit chips may be mounted directly on the capture pads. The capture pads are typically fabricated in the multilayer thin film wiring substrate. Alternatively, they may also be fabricated in the thick film multilayer ceramic substrate. One or more rows of capture pads may also be formed along one or more edges of the substrate face, so that an edge connector may be attached at the substrate edge to provide external electrical connections.
As is well known to those having skill in the art, the ceramic green sheets shrink during the sintering process. This shrinkage is not uniform or predictable across the face of the multilayer ceramic substrate. For example, shrinkage of 12% .+-.3% may be encountered.
Techniques have been developed to reduce the amount and variability of this shrinkage. See for example U.S. Pat. No. 4,677,254 to Boss et al. entitled Process for Minimizing Distortion in Multilayer Ceramic Substrates and the Intermediate Unsintered Green Ceramic Substrate Produced Thereby. However, notwithstanding this and other attempts, nonuniform shrinkage continues to be a problem. Other techniques have been developed in an attempt to accommodate the variability of shrinkage which occurs during the fabrication of the multilayer ceramic substrate. See for example U.S. Pat. No. 4,562,513 to Arnold et al. entitled Process for Forming a High Density Metallurgy System on a Substrate and Structure Thereof.
Alignment between the capture pads on the substrate face and the conductor filled vias which are electrically connected thereto, must be ensured in order to provide the required electrical connection between the capture pads and the conductor filled vias within the substrate. In order to accommodate the variability in position of the conductor filled vias, due to the nonuniform shrinkage of the multilayer ceramic substrate, oversized capture pads are typically used. In particular, the capture pads are all made large enough to accommodate the worst case variation in via position. Thus, the capture pad will always electrically contact the associated via even if the worst case variability in position is encountered. The capture pads are of the same size, which is set by the worst case via position variation. Because the worst case via position variation must be accommodated, the oversized capture pads limit the number of capture pads which can be formed on the face of a multilayer ceramic substrate. The number of vias which can be formed at the face of the multilayer ceramic substrate is also limited. Connection density is reduced correspondingly.